? 2004 fairchild semiconductor corporation ds009453 www.fairchildsemi.com january 1988 revised january 2004 74f843 9-bit transparent latch 74f843 9-bit transparent latch general description the 74f843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and pro- vide extra data width for wider address/data paths or buses carrying parity. features 3-state output ordering code: logic symbols ieee connection diagram order number package number package description 74F843SCX m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide
www.fairchildsemi.com 2 74f843 unit loading/fan out functional description the 74f843 consists of nine d-type latches with 3-state outputs. the flip-flops appear transparent to the data when latch enable (le) is high. this allows asynchronous operation, as the output transition follows the data in transi- tion. on the le high-to-low transition, the data that meets the setup times is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the bus output is in the high impedance state. in addition to the le and oe pins, the 74f843 has a clear (clr ) pin and a preset (pre ). these pins are ideal for parity bus interfac- ing in high performance systems. when clr is low, the outputs are low if oe is low. when clr is high, data can be entered into the latch. when pre is low, the out- puts are high if oe is low. preset overrides clr . function table h = high voltage level l = low voltage level x = immaterial z = high impedance nc = no change logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. pin names description u.l. input i ih /i il high/low output i oh /i ol d 0 ?d 8 data inputs 1.0/1.0 20 a/ ? 0.6 ma oe output enable input 1.0/1.0 20 a/ ? 0.6 ma le latch enable 1.0/1.0 20 a/ ? 0.6 ma clr clear 1.0/1.0 20 a/ ? 0.6 ma pre preset 1.0/1.0 20 a/ ? 0.6 ma o 0 ?o 8 3-state data outputs 150/40 ? 3 ma/24 ma inputs internal output function clr pre oe le d q o h h x x x x z high z hhhhl l z high z hhhhh h z high z h h h l x nc z latched h h l h l l l transparent h h l h h h h transparent h h l l x nc nc latched h l l x x h h preset l h l x x l l clear lllxx h h preset l h h l x l z latched hlhlx h z latched
3 www.fairchildsemi.com 74f843 absolute maximum ratings (note 1) recommended operating conditions note 1: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. note 2: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics storage temperature ? 65 c to + 150 c ambient temperature under bias ? 55 c to + 125 c junction temperature under bias ? 55 c to + 150 c v cc pin potential to ground pin ? 0.5v to + 7.0v input voltage (note 2) ? 0.5v to + 7.0v input current (note 2) ? 30 ma to + 5.0 ma voltage applied to output in high state (with v cc = 0v) standard output ? 0.5v to v cc 3-state output ? 0.5v to + 5.5v current applied to output in low state (max) twice the rated i ol (ma) free air ambient temperature 0 c to + 70 c supply voltage + 4.5v to + 5.5v symbol parameter min typ max units v cc conditions v ih input high voltage 2.0 v recognized as a high signal v il input low voltage 0.8 v recognized as a low signal v cd input clamp diode voltage ? 1.2 v min i in = ? 18 ma v oh output high 10% v cc 2.5 i oh = ? 1 ma voltage 10% v cc 2.4 vmin i oh = ? 3 ma 5% v cc 2.7 i oh = ? 1 ma 5% v cc 2.7 i oh = ? 3 ma v ol output low voltage 10% v cc 0.5 v min i ol = 24 ma i ih input high current 5.0 amaxv in = 2.7v i bvi input high current 7.0 amaxv in = 7.0v breakdown test i cex output high 50 amaxv out = v cc leakage current v id input leakage 4.75 v 0.0 i id = 1.9 a tes t all other pins grounded i od output leakage 3.75 a0.0 v iod = 150 mv circuit current all other pins grounded i il input low current ? 0.6 ma max v in = 0.5v i ozh output leakage current 50 amaxv out = 2.7v i ozl output leakage current ? 50 amaxv out = 0.5v i os output short-circuit current ? 60 ? 150 ma max v out = 0v i zz bus drainage test 500 a0.0vv out = 5.25v i cc power supply current 65 90 ma max
www.fairchildsemi.com 4 74f843 ac electrical characteristics ac operating requirements symbol parameter t a = + 25 ct a = 0 c to + 70 c units v cc = + 5.0v v cc = + 5.0v c l = 50 pf c l = 50 pf min typ max min max t plh propagation delay 2.5 5.4 8.0 2.0 9.0 ns t phl d n to o n 1.5 4.2 6.5 1.5 7.0 t plh propagation delay 5.0 8.5 12.0 4.5 13.5 ns t phl le to o n 2.0 4.7 7.5 2.0 8.0 t plh propagation delay 3.0 7.3 10.0 2.5 11.0 ns pre to o n t phl propagation delay 3.0 6.9 10.0 2.5 11.0 ns clr to o n t pzh output enable time 2.5 5.0 8.5 2.0 9.5 ns t pzl oe to o n 2.5 6.1 9.0 2.0 10.0 t phz output disable time 1.0 3.6 6.5 1.0 7.5 ns t plz oe to o n 1.0 3.4 6.5 1.0 7.5 symbol parameter t a = + 25 ct a = 0 c to + 70 c units v cc = + 5.0v v cc = + 5.0v min max min max t s (h) setup time, high or low 2.0 2.5 ns t s (l) d n to le 2.0 2.5 t h (h) hold time, high or low 2.5 3.0 t h (l) d n to le 3.0 3.5 t w (h) le pulse width, high 4.0 4.0 ns t w (l) pre pulse width, low 5.0 5.0 ns t w (l) clr pulse width, low 5.0 5.0 ns t rec pre recovery time 10.0 10.0 ns t rec clr recovery time 12.0 13.0 ns
5 www.fairchildsemi.com 74f843 9-bit transparent latch physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m24b fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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